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LH1691
LH1691
DESCRIPTION
The LH1691 is a 240-output TFT-LCD gate driver IC.
240-output TFT-LCD Gate Driver IC
PIN CONNECTIONS
258-PIN TCP TOP VIEW
FEATURES
* Number of LCD drive outputs : 240 * LCD drive output sequence : Output shift direction can be selected OG1/OG240 or OG240/OG1 * Cascade connection : Max. 2 cascades (internal counting system) * Usable with both positive/negative power supplies * Output mode selection - Normal mode (1-pulse scanning) - Continuous 2-pulse mode (2-pulse scanning) - Jumping 2-pulse mode (2-pulse scanning) * LCD drive voltage : +16.0 to +33.0 V * Operating temperature : -30 to +85 C * Package : 258-pin TCP (Tape Carrier Package)
VDD VEE VSS VCC VLS TEST1 TEST2 CKV SPV CE R/L MODE1 MODE2 VLS VCC VSS VEE VDD 258 257 256 255 254 253 252 251 250 249 248 247 246 245 244 243 242 241
1 OG1 2 OG2 3 OG3
CHIP SURFACE
238 OG238 239 OG239 240 OG240
NOTE :
Doesn't prescribe TCP outline.
In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.
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LH1691
PIN DESCRIPTION
PIN NO. 1 to 240 241, 258 242, 257 243, 256 244, 255 245, 254 246, 247 248 249 250 251 252, 253 SYMBOL OG1-OG240 VDD VEE VSS VCC VLS MODE2, MODE1 R/L CE SPV CKV TEST2, TEST1 I/O O - - - - - I I I I I I DESCRIPTION LCD drive output pins Power supply pins for LCD drive Power supply pins for LCD drive Power supply pins for logic system Power supply pins for logic system Power supply pins for input level shifter Output mode selection pins Pin for selecting bi-directional shift register and setting cascade sequence Cascade sequence setting pin Vertical scanning start pulse input pin Vertical shift clock input pin IC test pins
BLOCK DIAGRAM
MODE2 246 MODE1 247 R/L 248 CE 249 SPV 250 CKV 251 TEST2 252 TEST1 253 1 CONTROL LOGIC 1 1
BI-DIRECTIONAL SHIFT REGISTER 240
LEVEL SHIFTER 240
OUTPUT CIRCUIT 240
241 258 245 254 244 255 242 257 243 256 VDD VDD VLS VLS VCC VCC VEE VEE VSS VSS
1 OG1
240 OG240
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LH1691
FUNCTIONAL OPERATIONS OF EACH BLOCK
BLOCK Control Logic Bi-directional Shift Register Level Shifter Output Circuit FUNCTION Used to create signals necessary for mode selecting signal, cascade sequence setting signal and for operation of bi-directional shift register. Used as transfer circuit of LCD drive output start signal. It is possible to set LCD drive output sequence of OG1/OG240 direction or OG240/OG1 direction. Used as circuit which shifts LCD drive output signals transferred by bi-directional shift register to VDD-VEE level. Configured with output buffers to output VDD-VEE level.
INPUT/OUTPUT CIRCUITS
VLS
I
VSS
,
To Internal Circuit
Level Shifter Internal Logic (VLS-0 V/VCC-VSS) (VCC-VSS)
Applicable pins CKV, SPV, CE, R/L, MODE1, MODE2, TEST1, TEST2
Fig. 1 Input Circuit
VDD
O
From Internal Circuit (VDD-VEE)
VEE
Applicable pins OG1-OG240
Fig. 2 Output Circuit
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LH1691
FUNCTIONAL DESCRIPTION Pin Functions
SYMBOL VDD VLS VCC VEE VSS CKV SPV FUNCTION Used as power supply pin for high level LCD drive. Used as power supply pin for input level shifters. Used as power supply pin for logic system, normally connected to VSS + 5.0 V. Used as power supply pin for low level LCD drive. Used as logic system power supply pin. Used as vertical shift clock pulse input pin. Used as vertical scanning start pulse input pin. (At least, input one cycle of CKV during "L" period of SPV.) Used as input pins for selecting output mode. Output mode is set as shown in the table below by setting MODE1 pin and MODE2 pin. MODE1 MODE1 MODE2 H L H L MODE2 H H L L Output mode Normal mode (1-pulse scanning) Continuous 2-pulse mode Jumping 2-pulse mode Set all outputs to VEE level.
Used as input pin for selecting the shift direction of bi-directional shift register and for setting the sequence of cascade connection. R/L LCD drive outputs shift from OG1 to OG240 when set to "H". LCD drive outputs shift from OG240 to OG1 when set to "L". At the same time, cascade sequence is set as shown in the table below. Used as input pin for setting of chip cascade sequence. (Max. 2 cascades) Cascade sequence CE R/L = "H" R/L = "L" H L 1st 2nd 2nd 1st
CE
TEST1 TEST2 OG1-OG240
With above setting, sets the cascade sequence signal inside the IC. Used as input pins for IC testing. Must be set to "H". Used as output pins for LCD drive output, and which output data at 2 levels. * Selecting data is output at VDD level . * Non-selecting data is output at VEE level .
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LH1691
Functional Operations
(1) Example of Cascade Sequence
OG1 CE = "H" OG240 TFT-LCD Panel OG1 CE = "L" OG240 Scanning Direction When R/L = "L". Scanning Direction When R/L = "H".
* At this time, normal mode (scanning with 1 pulse) is set when MODE1 = "H" and MODE2 = "H", jumping 2-pulse mode (scanning with 2 pulses) is set when MODE1 = "H" and MODE2 = "L", continuous 2-pulse mode (scanning with 2 pulses) is set when MODE1 = "L" and MODE2 = "H", and output VEE level is set when MODE1 = "L" and MODE2 = "L".
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LH1691
(2) Example of Input/Output Timing (For 1st Cascade Sequence)
CKV SPV
OG1 OG2 OG3 OG1 OG2 OG3 OG1 OG2 OG3
OG240 OG239 OG238 OG240 OG239 OG238 OG240 OG239 OG238
(1-pulse Mode)
(Jumping 2-pulse Mode)
(Continuous 2-pulse Mode)
R/L = "H" R/L = "L"
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LH1691
PRECAUTIONS
Precautions when connecting or disconnecting the power supply This IC has a high-voltage LCD driver, so it may be permanently damaged by a high current which may flow if voltage is supplied to the LCD drive power supply while the logic system power supply is floating. Therefore, when connecting the power supply, observe the following sequence. Logic system power supply (VLS) or internal logic system power supply (VSS, VCC; VCC > VSS) / logic input / LCD drive power supply (VEE, VDD) It is possible to set voltage VEE to the same as VSS. When connecting the power supply when VEE = VSS, observe the following sequence and the recommended sequence figure shown below. Logic system power supply (VLS), internal logic system power supply (VSS, VCC; VCC > VSS) and low-level LCD drive power supply (VEE) / logic input / high-level LCD drive power supply (VDD) When disconnecting the power supply, follow the reverse sequence. Since the logic state of the internal circuit is unstable immediately after the logic system power is supplied, input CKV and SPV while initializing the internal circuit (minimum input clock number is 240 CKV). MODE1 and MODE2 should be set to "L" during the initializing period for setting the LCD drive output to VEE level.
VDD VLS Input 0V
VCC VSS, VEE
Input pin setting Input pins other than CKV and SPV must be set to "H" or "L" level.
Maximum ratings When connecting or disconnecting the power, this IC must be used within the range of the absolute maximum ratings.
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LH1691
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL VDD VLS Supply voltage VCC - VSS VEE - VSS VDD - VEE (VSS) Input voltage Storage temperature VIN TSTG APPLICABLE PINS VDD VLS VCC, VSS VEE, VSS VDD, VEE, VSS CKV, SPV, CE, R/L, MODE1, MODE2, TEST1, TEST2 RATING -0.3 to +35.0 -0.3 to +7.0 -0.3 to +7.0 -0.3 to +35.0 -0.3 to +35.0 -0.3 to VLS + 0.3 -45 to +125 UNIT V V V V V V C 1, 2 NOTE
NOTES :
1. TA = +25 C 2. The maximum applicable voltage on any pin with respect to 0 V.
RECOMMENDED OPERATING CONDITIONS
PARAMETER SYMBOL VDD VLS VEE - VSS VDD - VEE (VSS) VIN TOPR MIN. +5.5 +3.0 0 +16.0 0 -30 +25.0 TYP. +9.0 +5.0 +5.0 MAX. +33.0 +5.5 +5.5 +11.0 +33.0 VLS +85 UNIT V V V V V V C 1, 2 NOTE
Supply voltage
VCC - VSS +3.0
Input voltage Operating temperature
NOTES :
1. The applicable voltage on any pin with respect to 0 V. 2. Ensure that voltages are set as follows. VSS, VEE 0 V VCC - VSS = VLS0.2 V (For 3.3 V specifications) VCC - VSS = VLS0.3 V (For 5.0 V specifications) VCC VLS
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LH1691
When power supply pins are set as shown below, the LH1691 can output positive voltage and negative voltage to LCD drive output. Example 1 : For Positive Voltage Output
VDD LCD Drive Output
VLS, VCC VSS, VEE (0 V)
Input
Internal Logic
Example 2 : For Negative Voltage Output
VDD, VLS 0V Input LCD Drive Output
VCC VSS, VEE
Internal Logic
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LH1691
ELECTRICAL CHARACTERISTICS DC Characteristics
PARAMETER Input "Low" voltage Input "High" voltage Output "Low" voltage Output "High" voltage Input "Low" current Input "High" current SYMBOL CONDITIONS VIL VIH VOL VOH IIL IIH IDD Supply current (1) ILS ICC IEE IDD Supply current (2) ILS ICC IEE IDD Supply current (3) ILS ICC IEE For continuous 2-pulse mode For jumping 2-pulse mode For 1-pulse mode IOL = 0.4 mA
(VLS = +3.30.3 V (= VCC - VSS), TOPR = -30 to +85 C)
APPLICABLE PINS CKV, SPV, MODE1, MODE2, CE, R/L OG1-OG240 IOH = -0.4 mA VI = 0 V CKV, SPV, MODE1, VI = VLS MODE2, CE, R/L MIN. 0.8VLS VEE + 0.4 VDD - 0.4 5.0 5.0 50 100 50 40 100 200 60 40 100 200 60 40 TYP. MAX. 0.2VLS UNIT V V V V A A A A A A A A A A A A A A 4 3 1 NOTE
2
NOTES :
1. All input pins : 3.3 V 2. CKV : Frequency = 31 kHz, "L" period width tWL = 16.2 s SPV : Frequency = 60 Hz Other input pins : 3.3 V All output pins are opened. 3. CKV : Frequency = 31 kHz, "L" period width tWL = 16.2 s SPV : Frequency = 60 Hz MODE2 : 0 V Other input pins : 3.3 V All output pins are opened. 4. CKV : Frequency = 31 kHz, "L" period width tWL = 16.2 s SPV : Frequency = 60 Hz MODE1 : 0 V Other input pins : 3.3 V All output pins are opened.
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LH1691
(VLS = +5.00.5 V (= VCC - VSS), TOPR = -30 to +85 C)
PARAMETER Input "Low" voltage Input "High" voltage Output "Low" voltage Output "High" voltage Input "Low" current Input "High" current SYMBOL CONDITIONS VIL VIH VOL VOH IIL IIH IDD Supply current (1) ILS ICC IEE IDD Supply current (2) ILS ICC IEE IDD Supply current (3) ILS ICC IEE For continuous 2-pulse mode For jumping 2-pulse mode For 1-pulse mode IOL = 0.4 mA IOH = -0.4 mA VI = 0 V VI = VLS APPLICABLE PINS CKV, SPV, MODE1, MODE2, CE, R/L OG1-OG240 CKV, SPV, MODE1, MODE2, CE, R/L MIN. 0.8VLS VEE + 0.4 VDD - 0.4 5.0 5.0 50 150 80 40 100 300 100 40 100 300 100 40 TYP. MAX. 0.2VLS UNIT V V V V A A A A A A A A A A A A A A 4 2 1 NOTE
3
NOTES :
1. All input pins : 5 V 2. CKV : Frequency = 31 kHz, "L" period width tWL = 16.2 s SPV : Frequency = 60 Hz Other input pins : 5 V All output pins are opened. 3. CKV : Frequency = 31 kHz, "L" period width tWL = 16.2 s SPV : Frequency = 60 Hz MODE2 : 0 V Other input pins : 5 V All output pins are opened. 4. CKV : Frequency = 31 kHz, "L" period width tWL = 16.2 s SPV : Frequency = 60 Hz MODE1 : 0 V Other input pins : 5 V All output pins are opened.
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LH1691
AC Characteristics
PARAMETER Clock frequency "L" clock pulse width Clock rise time Clock fall time Data setup time Data hold time Pulse rise time Pulse fall time Output transfer delay time Output rise time Output fall time
(VLS = +3.30.3 V (= VCC - VSS), TOPR = -30 to +85 C)
APPLICABLE PINS MIN. 0.5 100 100 CKV, SPV SPV 100 300 100 100 3.0 CL = 500 pF OG1-OG240 1.0 1.0 TYP. MAX. 100 UNIT kHz s ns ns ns ns ns ns s s s
SYMBOL CONDITIONS fCKV tWL tRCKV tFCKV tSU tH tRSPV tFSPV tD tR tF
CKV
(VLS = +5.00.5 V (= VCC - VSS), TOPR = -30 to +85 C)
PARAMETER Clock frequency "L" clock pulse width Clock rise time Clock fall time Data setup time Data hold time Pulse rise time Pulse fall time Output transfer delay time Output rise time Output fall time SYMBOL CONDITIONS fCKV tWL tRCKV tFCKV tSU tH tRSPV tFSPV tD tR tF CL = 500 pF OG1-OG240 CKV, SPV SPV 100 300 100 100 2.0 1.0 1.0 APPLICABLE PINS MIN. 0.5 100 100 TYP. MAX. 100 UNIT kHz s ns ns ns ns ns ns s s s
CKV
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LH1691
Timing Chart
tFCKV CKV tFSPV SPV 90% 10% 90% 10% tSU tWL tRCKV 90% 10% tH tRSPV 90% 10% tD tD 50% 50% 50% 50% 50% 50%
90% 50% OG1-OG240 (1-pulse Mode) tD 10% tR tD
90% 50% 10% tF
50% OG1-OG240 (Continuous 2-pulse Mode) tD tD
50%
50% OG1-OG240 (Jumping 2-pulse Mode)
50%
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PACKAGE
LH1691F
Film center Device center
MODE2
MODE1
TEST2
COM1 R/L VDD VCC VCC VDD 63.9490.12 26.750.7 36.00.06 [34.0 (E.L.)] 28.0 (SL) P1.20 x (23 - 1) = 26.40.05 W0.400.02 2-O2.7 (Cu) 2-O1.9 (PI) 2-O1.5 (Cu hole) CKV SPV VSS VEE VEE VSS VLS VLS CE
COM1
COM2
COM3
COM4
COM4
O2.0 (Good device hole)
2.2 (SR) 2.0 (SL)
5.00.7 [5.0 (E.L.)]
45
Sprocket center Chip center 4.7 MAX. (Resin area)
5.5
8.5 (SL)
UPILEX is a trademark of UBE INDUSTRIES, LTD..
19.1MAX. (Resin area)
2.5 (SL)
0.083 (SL)
3.5 (SL)
5.7 (SR) 7.70.05 [9.2 (E.L.)] [14.2 (E.L.)]
14
P0.17 x (248 - 1) = 41.990.08 W0.0950.02 21.4 (SR) 42.90.08 (Mark) 0.9 (SL) 21.8 (SL) [44.0 (E.L.)] (47.0) OG238 OG239 OG240 DUMMY COM2 COM1 COM1
1.9810.05 21.4 (SR) 21.8 (SL) 0.9 (SL) 0.3MAX. Pattern side 0.75MAX. Backside 0.095 COM4 COM4 COM3 DUMMY OG1 OG2 OG3 1.2MAX. Total [0.15]
1.9810.05
4.750.05
[3.5TYP. (3.2MIN.)]
0.40.02 0.60.02
0.40.02
0.60.02
0.05
o Tape Specification
Tape width Tape type Perforation pitch 70 mm Wide 4 pitches
o Tape Material
Substrate Adhesive Cu foil [thickness] Solder resist UPILEX S75 #7100 SLP 18 m Epoxy resin (Unit : mm)
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